Apparatus with an internal-operation management mechanism

ABSTRACT

Methods, apparatuses, and systems related to scheduling internal operations are described. An apparatus detects a condition associated with repeated accesses to a memory address and/or region. In response to detection of the condition, the apparatus generates a scheduling output that secures a scheduled duration of inactivity for commanded operations. The apparatus initiates execution of one or more internal operations during the scheduled duration.

TECHNICAL FIELD

The disclosed embodiments relate to devices, and, in particular, tosemiconductor memory devices with an internal-operation managementmechanism.

BACKGROUND

An apparatus (e.g., a processor, a memory device, a memory system, or acombination thereof) can include one or more semiconductor circuitsconfigured to store and/or process information. For example, theapparatus can include a memory device, such as a volatile memory device,a non-volatile memory device, or a combination device. Memory devices,such as dynamic random-access memory (DRAM), can utilize electricalenergy to store and access data. For example, the memory devices caninclude Double Data Rate (DDR) RAM devices that implement DDRinterfacing scheme (e.g., DDR4, DDR5, etc.) for high-speed datatransfer.

With technological advancements in other areas and increasingapplications, the market is continuously looking for faster, moreefficient, and smaller devices. To meet the market demand, thesemiconductor devices are being pushed to the limit. In view of theever-increasing commercial competitive pressures, along with growingconsumer expectations and the desire to differentiate products in themarketplace, it is increasingly desirable that answers be found to theseproblems. Additionally, the need to reduce costs, improve efficienciesand performance, and meet competitive pressures adds an even greaterpressure to find answers to these problems.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a computing system in accordance with anembodiment of the present technology.

FIG. 2 is a block diagram of a computing system in accordance with anembodiment of the present technology.

FIG. 3 is a block diagram of an apparatus in accordance with anembodiment of the present technology.

FIG. 4 is an example circuit diagram of a detection circuit inaccordance with an embodiment of the present technology.

FIG. 5 is an example timing diagram in accordance with an embodiment ofthe present technology.

FIG. 6 is a flow diagram illustrating an example method of operating anapparatus in accordance with an embodiment of the present technology.

FIG. 7 is a schematic view of a system that includes an apparatus inaccordance with an embodiment of the present technology.

DETAILED DESCRIPTION

As described in greater detail below, the technology disclosed hereinrelates to an apparatus, such as memory systems, systems with memorydevices, related methods, etc., for managing memory-internal operations,such as refresh operations (e.g., row hammer refresh (RHR) operations).As described detail below, an apparatus (e.g., a memory system/device,such as a DRAM module) can detect triggering conditions, such asrepeated access/activation of a memory or a region/grouping of memorycells. Upon detecting the triggering condition, the apparatus cangenerate a scheduling output configured to establish a time period forexecuting the memory-internal operations.

As memory devices become smaller and faster, storage circuits canexperience data degradation due to the adverse effects of repeatedaccess, such as for repeated reads from and/or repeated writes to thesame address or addresses within a region. As an illustrated example,for “row hammer” type of memory degradation, stored charge can be lostin the cells of a word line when an adjacent or nearby word line isrepeatedly activated/deactivated over a short period of time. Thepotential for adverse row hammer effects is further worsened forphysically smaller memory devices, in which the distance betweenadjacent word lines decreases. To offset the potential for charge loss,the memory devices can perform RHRs to refresh (e.g., compensate for theloss by recharging) the word lines that are adjacent to a hammered wordline.

Conventional devices have implemented the RHRs between or in parallelwith commanded operations, such as by “stealing” one or more operatingcycles. However, the time window for performing the RHRs are furtherdecreasing as the memory devices and/or the hosts become faster. Forexample, DRAM devices are synchronous and perform commanded operationsin real-time. In other words, the DRAM devices must write, read, andrefresh data at the host's command. As such, as the overall operatingspeeds increase, the time used to perform the RHRs are decreasing at thesame rate. Further, occurrences of pathological patterns or usage (e.g.,row hammer or other repetitive access to same address or region) thatrequire/trigger the memory-internal operations are increasing infrequency with the growth of technology. Thus, the memory-internaloperations need to be executed more frequently, thereby increasing thenumber of failures and/or increasing the errors/issues associated withback-to-back internal operations.

As described in detail below, embodiments of the present technology canmanage the time-window for performing the memory-internal operations. Insome embodiments, the apparatus can detect one or more predeterminedtriggering conditions and generate the scheduling output by forcingerror conditions, such as by reporting to or causing errors for a hostindependent of an occurrence of an associated error condition. Forexample, the apparatus can cause a system failure or report anassociated error for a parity failure (e.g., a column address (CA)parity communication failure, a command parity failure, a cyclicredundancy check (CRC) failure, etc.), a data write error, a data readerror, and/or a temperature failure. Also, the apparatus can alter data,such as by flipping one or more DQs, to cause a system failure. Based onthe scheduling output, the host can enter into an error recovery modeduring a recovery time (e.g., a predetermined duration) and resend oneor more commands, data, and/or addresses. The apparatus can schedule andexecute the memory-internal operations during the recovery time.Accordingly, the apparatus can secure a set duration to execute thememory-internal operations, thereby decreasing/eliminating errors causedby insufficient execution times and/or back-to-back implementations ofthe memory-internal operations.

FIG. 1 is a block diagram of a computing system 100 in accordance withan embodiment of the present technology. The computing system 100 caninclude a host 102, such as a processor, a central processing unit(CPU), a graphics processing unit (GPU), and/or other computing device,coupled to a memory system 104. The memory system 104 can include a setof devices that are together configured to store and provide access toelectronic data. For example, the memory system 104 can includenon-volatile memory modules, volatile memory modules, combinationalsystems, and/or other memory cards/systems.

In some embodiments, the host 102 and the memory system 104 can becommunicatively coupled via a command-address connection 112 (e.g., acommand and address bus), an alert connection 114 (e.g., an Alert linefor ALERT #signal for DDR4/5 protocol), and/or a data connection 116(e.g., a data (DQ) bus). The host 102 and the memory system 104 cancommunicate commands, such as for writes, reads, and/or refreshes, andassociated addresses over the command-address connection 112. The host102 and the memory system 104 can communicate content (e.g., write dataand/or read data) over the data connection 116. The alert connection 114can be used to communicate detection of various conditions between thehost 102 and the memory system 104. For example, the host 102 and thememory system 104 can communicate the alert signal to reportcommunication errors on the command-address connection 112 and/or thedata connection 116.

The host 102 can include circuitry to handle various errors. In someembodiments, the host 102 can include an error handler 122 and/or acommand queue 124. The error handler 122 can be configured to detect anerror, track a timing associated with the error, and/or control aninterface with the memory system 104 in responding to the error. Forexample, the error handler 122 can wait a predetermined period of timeand retransmit one or more commands, addresses, write/read dataassociated with or following the error. The command queue 124 can tracka predetermined number of operation commands (e.g., reads, writes,and/or refreshes) issued or to-be issued by the host 102. The host 102can use the tracked commands for the error-based retransmissions.

The memory system 104 can include one or more devices for storing andproviding access to information. The memory system 104 can include oneor more devices, such as one or more storage devices 142 (e.g., storagedevices 142 _(1-n)) and/or a register device 144. The storage devices142 can include memory cells configured to retain an electrical chargeand/or a magnetic state. The storage devices 142 can vary an amount ofthe electrical charge and/or the magnetic state to store the data.Further, the storage devices 142 can determine and report the amount ofthe electrical charge and/or the magnetic state in reading the data. Theregister device 144 can manage an interaction between the storagedevices 142 and the host 102. For example, the register device 144 canmanage timing, one or more clock signals, and/or register control. As anillustrative example, the memory system 104 can be a memory module(e.g., a single in-line memory module (SIMM) or a dual in-line memorymodule (DIMM)) and the storage devices 142 can be RAM chips. In someembodiments, the register device 144 can include a register clock driver(RCD) chip.

In some embodiments, the register device 144 can include a schedulemanagement circuit 152 configured to manage the time-window forperforming the memory-internal operations (e.g., refresh operations,such as RHRs). The schedule management circuit 152 can detect one ormore predetermined conditions associated with the memory-internaloperations, such as via a detection circuit 154 (e.g., a row-hammerdetection circuit). In response to the detection, the schedulemanagement circuit 152 can determine a scheduled duration (via, e.g., ascheduling circuit 156) for executing one or more memory-internaloperations.

The scheduling circuit 156 can be configured to generate schedulingoutputs that interact with the host 102 to secure time windows for thememory system 104 to execute the memory-internal operations. Forexample, the scheduling circuit 156 can generate the scheduling outputsthat force error conditions, such as by reporting to or causing errorsfor the host 102 independent of an occurrence of an actual errorcondition. The scheduling circuit 156 can include one or moretransistors configured to drive one or more outputs (via, e.g., thealert connection 114 and/or the data connection 116) to a predeterminedstage/level based on the detection. Accordingly, the scheduling circuit156 can generate and send an ALERT #signal and/or adjust communicateddata for CA parity communication failures, CRC failures, hightemperature reports, flipping DQs, command CA parity errors, data writeand/or read CRC errors, and/or other alert messages.

FIG. 2 is a block diagram of a computing system 200 in accordance withan embodiment of the present technology. The computing system 200 can besimilar to the computing system 100 of FIG. 1. For example, thecomputing system 200 can include a host 202 (e.g., a processor, acentral processing unit (CPU), a graphics processing unit (GPU), and/orother computing device) and a memory system 204 (e.g., a non-volatilememory module, a volatile memory module, a combinational system, and/orother memory card/system). Also, the host 202 and the memory system 204can be communicatively coupled via a command-address connection 212(e.g., a command and address bus), an alert connection 214 (e.g., anAlert line for ALERT #signal for DDR4/5 protocol), and/or a dataconnection 216 (e.g., a data (DQ) bus). The host 202 can includecircuitry to handle various errors, such as an error handler 222 and/ora command queue 224, similar to the host 102 of FIG. 1, the errorhandler 122 of FIG. 1 and/or the command queue 124 of FIG. 1.

The memory system 204 can include one or more storage devices 242 (e.g.,storage devices 242 _(1-n), such as RAM chips) that include memory cellsconfigured to retain an electrical charge and/or a magnetic state. Thestorage devices 242 can vary an amount of the electrical charge and/orthe magnetic state to store the data. Further, the storage devices 242can determine and report the amount of the electrical charge and/or themagnetic state in reading the data. In some embodiments, the alertconnection 214 can include a shared bus that couple the storage devices242 to the host 202.

In one or more embodiments, each of the storage devices 242 can includea schedule management circuit 252 configured to manage the time-windowfor performing the memory-internal operations (e.g., refresh operations,such as RHRs). The schedule management circuit 252 can detect one ormore predetermined conditions (e.g., row hammer or other repeated accessconditions) associated with the memory-internal operations, such as viaa detection circuit 254 (e.g., a row-hammer detection circuit). Inresponse to the detection, the schedule management circuit 252 candetermine a scheduled duration (via, e.g., a scheduling circuit 256) forexecuting one or more memory-internal operations.

The scheduling circuit 256 can be configured to generate schedulingoutputs that interact with the host 202 to secure time windows for thememory system 204 to execute the memory-internal operations. Forexample, the scheduling circuit 256 can generate the scheduling outputsthat force error conditions, such as by reporting to or causing errorsfor the host 202 independent of an occurrence of an actual errorcondition. The scheduling circuit 256 can include one or moretransistors configured to drive one or more outputs (via, e.g., thealert connection 214 and/or the data connection 216) to a predeterminedstage/level based on the detection. Accordingly, the scheduling circuit256 can generate and send an ALERT #signal and/or adjust communicateddata for CA parity communication failures, CRC failures, hightemperature reports, flipping DQs, command CA parity errors, data writeand/or read CRC errors, and/or other alert messages.

FIG. 3 is a block diagram of a device 300 (e.g., a semiconductor dieassembly, including a 3DI device or a die-stacked package) in accordancewith an embodiment of the present technology. For example, the device300 can include a DRAM (e.g., DDR3 DRAM, DDR4 DRAM, DDR5 DRAM, etc.), ora portion thereof that includes one or more dies/chips. In someembodiments, the device 300 can include synchronous DRAM (SDRAM) of DDRtype integrated on a single semiconductor chip. The device 300 cancorrespond to the storage devices 142 of FIG. 1 and/or the storagedevices 242 of FIG. 2.

The device 300 may include an array of memory cells, such as memoryarray 350. The memory array 350 may include a plurality of banks (e.g.,banks 0-15), and each bank may include a plurality of word lines (WL), aplurality of bit lines (BL), and a plurality of memory cells arranged atintersections of the word lines and the bit lines. Memory cells caninclude any one of a number of different memory media types, includingcapacitive, magnetoresistive, ferroelectric, phase change, or the like.The selection of a word line WL may be performed by a row decoder 340,and the selection of a bit line BL may be performed by a column decoder345. Sense amplifiers (SAMP) may be provided for corresponding bit linesBL and connected to at least one respective local I/O line pair(LIOT/B), which may in turn be coupled to at least respective one mainI/O line pair (MIOT/B), via transfer gates (TG), which can function asswitches. The memory array 350 may also include plate lines andcorresponding circuitry for managing their operation.

The device 300 may employ a plurality of external terminals that includecommand and address terminals coupled to a command bus and an addressbus to receive command signals (CMD) and address signals (ADDR),respectively. The device 300 may further include a chip select terminalto receive a chip select signal (CS), clock terminals to receive clocksignals CK and CKF, data clock terminals to receive data clock signalsWCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, power supplyterminals VDD, VSS, and VDDQ.

The command terminals and address terminals may be supplied with anaddress signal and a bank address signal (not shown in FIG. 3) fromoutside. The address signal and the bank address signal supplied to theaddress terminals can be transferred, via a command/address inputcircuit 305, to an address decoder 310. The address decoder 310 canreceive the address signals and supply a decoded row address signal(XADD) to the row decoder 340, and a decoded column address signal(YADD) to the column decoder 345. The address decoder 310 can alsoreceive the bank address signal and supply the bank address signal toboth the row decoder 340 and the column decoder 345.

The command and address terminals may be supplied with command signals(CMD), address signals (ADDR), and chip select signals (CS), from amemory controller. The command signals may represent various memorycommands from the memory controller (e.g., including access commands,which can include read commands and write commands). The chip selectsignal may be used to select the device 300 to respond to commands andaddresses provided to the command and address terminals. When an activechip select signal is provided to the device 300, the commands andaddresses can be decoded and memory operations can be performed. Thecommand signals may be provided as internal command signals ICMD to acommand decoder 315 via the command/address input circuit 305. Thecommand decoder 315 may include circuits to decode the internal commandsignals ICMD to generate various internal signals and commands forperforming memory operations, for example, a row command signal toselect a word line and a column command signal to select a bit line. Thecommand decoder 315 may further include one or more registers fortracking various counts or values (e.g., counts of refresh commandsreceived by the device 300 or self-refresh operations performed by thedevice 300).

Read data can be read from memory cells in the memory array 350designated by row address (e.g., address provided with an activecommand) and column address (e.g., address provided with the read). Theread command may be received by the command decoder 315, which canprovide internal commands to input/output circuit 360 so that read datacan be output from the data terminals DQ, RDQS, DBI, and DMI viaread/write amplifiers 355 and the input/output circuit 360 according tothe RDQS clock signals. The read data may be provided at a time definedby read latency information RL that can be programmed in the device 300,for example, in a mode register (not shown in FIG. 3). The read latencyinformation RL can be defined in terms of clock cycles of the CK clocksignal. For example, the read latency information RL can be a number ofclock cycles of the CK signal after the read command is received by thedevice 300 when the associated read data is provided.

Write data can be supplied to the data terminals DQ, DBI, and DMIaccording to the WCK and WCKF clock signals. The write command may bereceived by the command decoder 315, which can provide internal commandsto the input/output circuit 360 so that the write data can be receivedby data receivers in the input/output circuit 360, and supplied via theinput/output circuit 360 and the read/write amplifiers 355 to the memoryarray 350. The write data may be written in the memory cell designatedby the row address and the column address. The write data may beprovided to the data terminals at a time that is defined by writelatency WL information. The write latency WL information can beprogrammed in the device 300, for example, in the mode register (notshown in FIG. 3). The write latency WL information can be defined interms of clock cycles of the CK clock signal. For example, the writelatency WL information can be a number of clock cycles of the CK signalafter the write command is received by the device 300 when theassociated write data is received.

The power supply terminals may be supplied with power supply potentialsVDD and VSS. These power supply potentials VDD and VSS can be suppliedto an internal voltage generator circuit 370. The internal voltagegenerator circuit 370 can generate various internal potentials VPP, VOD,VARY, VPERI, and the like based on the power supply potentials VDD andVSS. The internal potential VPP can be used in the row decoder 340, theinternal potentials VOD and VARY can be used in the sense amplifiersincluded in the memory array 350, and the internal potential VPERI canbe used in many other circuit blocks.

The power supply terminal may also be supplied with power supplypotential VDDQ. The power supply potential VDDQ can be supplied to theinput/output circuit 360 together with the power supply potential VSS.The power supply potential VDDQ can be the same potential as the powersupply potential VDD in an embodiment of the present technology. Thepower supply potential VDDQ can be a different potential from the powersupply potential VDD in another embodiment of the present technology.However, the dedicated power supply potential VDDQ can be used for theinput/output circuit 360 so that power supply noise generated by theinput/output circuit 360 does not propagate to the other circuit blocks.

The clock terminals and data clock terminals may be supplied withexternal clock signals and complementary external clock signals. Theexternal clock signals CK, CKF, WCK, WCKF can be supplied to a clockinput circuit 320. The CK and CKF signals can be complementary, and theWCK and WCKF signals can also be complementary. Complementary clocksignals can have opposite clock levels and transition between theopposite clock levels at the same time. For example, when a clock signalis at a low clock level a complementary clock signal is at a high level,and when the clock signal is at a high clock level the complementaryclock signal is at a low clock level. Moreover, when the clock signaltransitions from the low clock level to the high clock level thecomplementary clock signal transitions from the high clock level to thelow clock level, and when the clock signal transitions from the highclock level to the low clock level the complementary clock signaltransitions from the low clock level to the high clock level.

Input buffers included in the clock input circuit 320 can receive theexternal clock signals. For example, when enabled by a clock/enablesignal from the command decoder 315, an input buffer can receive theclock/enable signals. The clock input circuit 320 can receive theexternal clock signals to generate internal clock signals ICLK. Theinternal clock signals ICLK can be supplied to an internal clock circuit330. The internal clock circuit 330 can provide various phase andfrequency controlled internal clock signals based on the receivedinternal clock signals ICLK and a clock enable (not shown in FIG. 3)from the command/address input circuit 305. For example, the internalclock circuit 330 can include a clock path (not shown in FIG. 3) thatreceives the internal clock signal ICLK and provides various clocksignals to the command decoder 315. The internal clock circuit 330 canfurther provide input/output (IO) clock signals. The IO clock signalscan be supplied to the input/output circuit 360 and can be used as atiming signal for determining an output timing of read data and theinput timing of write data. The IO clock signals can be provided atmultiple clock frequencies so that data can be output from and input tothe device 300 at different data rates. A higher clock frequency may bedesirable when high memory speed is desired. A lower clock frequency maybe desirable when lower power consumption is desired. The internal clocksignals ICLK can also be supplied to a timing generator and thus variousinternal clock signals can be generated.

The device 300 can be connected to any one of a number of electronicdevices capable of utilizing memory for the temporary or persistentstorage of information, or a component thereof. For example, a hostdevice of device 300 may be a computing device such as a desktop orportable computer, a server, a hand-held device (e.g., a mobile phone, atablet, a digital reader, a digital media player), or some componentthereof (e.g., a central processing unit, a co-processor, a dedicatedmemory controller, etc.). The host device may be a networking device(e.g., a switch, a router, etc.) or a recorder of digital images, audioand/or video, a vehicle, an appliance, a toy, or any one of a number ofother products. In one embodiment, the host device may be connecteddirectly to device 300, although in other embodiments, the host devicemay be indirectly connected to memory device (e.g., over a networkedconnection or through intermediary devices).

The device 300 can include a refresh control circuit 380 configured tocontrol refreshing of the information of the corresponding memory cellMC. For example, as inputs, the refresh control circuit 380 can receivethe decoded row address signal (XADD) from the address decoder 310, arefresh signal (AREF) from the command decoder 315, an active signal(ACT) and/or a precharge signal (Pre) from the command decoder 315, etc.The command decoder 315 can generate the active signal (ACT) (e.g., apulse signal) when the command signals (CMD) indicates row access (e.g.,active command). The command decoder 315 can generate the prechargesignal (Pre) (e.g., a pulse signal) when the command signal (CMD)indicates pre-charge. The command decoder 315 can generate the refreshsignal (AREF) (e.g., a pulse signal) when the command signal (CMD)indicates an auto-refresh command and/or a self-refresh entry command.In response to the self-refresh entry command, the refresh signal (AREF)can be activated cyclically at a desired interval until a self-refreshexit command is received. In some embodiments, in response to therefresh signal (AREF), the refresh control circuit 380 can generate arefresh row address (RXADD) to the row decoder 340, which initiates therefresh operation therein (e.g., by activating a predetermined word linein the memory cell array). Accordingly, the device 300 can implement arefresh operation (e.g., scheduled refreshes) to refresh (e.g., increasestored charges) targeted locations.

In some embodiments, the refresh control circuit 380 can include thedetection circuit 254 of FIG. 2 configured to control the RHR operation.The detection circuit 254 can be configured to detect row hammer andcontrol and/or schedule the RHR operation and refresh word lines thatare adjacent to hammered (e.g., accessed more than a threshold amount oftimes over a predetermined period since the last refresh operation) wordlines. For implementing the RHR, the refresh control circuit 380 cangenerate one or more RHR addresses that identify the victim row(s)(e.g., the row(s) adjacent to or within a distance from the hammeredrow).

The refresh control circuit 380 (e.g., the detection circuit 254) caninclude counters that track row access and logic configured to comparethe access count to a predetermined limit. When the access count reachesthe limit, the refresh control circuit 380 (e.g., the detection circuit254 and/or other circuits within the refresh control circuit 380) canidentify the corresponding row as the hammered row and adjacent row asthe victim row. Based on identifying the victim row, the refresh controlcircuit 380 can generate the address of the victim row as the RHRaddress.

The refresh control circuit 380 can provide a refresh address (e.g., theRHR address) to a decoder (e.g., the row decoder 340) for executing thememory-internal operation. The refresh control circuit 380 can alsoprovide detection flags to the input/output circuit 360 based ondetecting the predetermined conditions. The input/output circuit 360 caninclude the scheduling circuit 256 that generate the scheduling outputsbased on the detection flags. For example, the scheduling circuit 256can set the ALERT #and/or set one or more bits for the DATA signal, suchas for a check error, a communication error, data/command error, etc.described above.

FIG. 4 is an example circuit diagram of a detection circuit 400 (e.g.,an embodiment of the refresh control circuit 380 of FIG. 3, thedetection circuit 154 of FIG. 1, and/or the detection circuit 254 ofFIG. 2) in accordance with an embodiment of the present technology. Thedetection circuit 400 can receive a refresh signal (AREF), an activesignal (ACT), a pre-charge signal (Pre), a row address XADD, etc. fromother circuits, such as the address decoder 310 of FIG. 3 and/or thecommand decoder 315 of FIG. 3.

In some embodiments, the detection circuit 400 can include a samplingsignal generator 402 and/or a shift register 404. The sampling signalgenerator 402 can be configured to generate a first sampling signal(S1). The shift register 404 can be configured to implement shiftoperations synchronized with the first sampling signal (S1).

The sampling signal generator 402 can randomly extract the active signal(ACT) or the pre-charge signal (Pre), which is generated in response toan active command or a precharge command. The sampling signal generator402 can output the signal as the first sampling signal (S1). The randomextraction can be configured to control the sampling rate that optimizesthe reliability of the RHR operations. The sampling signal generator 402can control the sampling rate based on the appearance frequency ofhammer addresses, the number of stages of the shift register 404, etc.

In some embodiments, the shift register 404 can include n-stages offlip-flop circuits (FF_1 to FF_n) in cascade connection for latching therow addresses (XADD). In other words, an output node of the flip-flopcircuit of a former stage can be connected to an input node of theflip-flop circuit of a subsequent stage. The first sampling signal (S1)can be commonly input to clock nodes of the flip-flop circuits. As aresult, when the first sampling signal (S1) is activated, the currentrow address (XADD) can be latched by the flip-flop circuit FF_1 of afirst stage, and the row addresses (XADD) latched by the flip-flopcircuits FF_1 to FF_n−1 can be respectively shifted to the flip-flopcircuits FF_2 to FF_n of next stages. The row address (XADD) latched bythe flip-flop circuit FF_n, which is a last stage, can be discarded inresponse to activation of the first sampling signal (S1).

The row addresses (XADD) latched by the flip-flop circuits FF_1 to FF_ncan be supplied to first-side input nodes of corresponding comparatorcircuits XOR_1 to XOR_n, respectively. The current row address (XADD)can be supplied to second-side input nodes of the comparator circuitsXOR_1 to XOR_n. As a result, if the current row address (XADD) matchesany of the row addresses (XADD) latched by the flip-flop circuits FF_1to FF_n, the output of the comparator circuit XOR_1 to XOR_n thereof canbe activated to a low level. Accordingly, a match signal (Match) outputfrom a NAND 406 can be activated to a high level.

The match signal (Match) and the first sampling signal (S1) can besupplied to an AND 408. When both of the match signal (Match) and thefirst sampling signal (S1) are activated to the high level, a secondsampling signal (S2) output from the AND 408 can be activated to thehigh level. More specifically, if the row address (XADD) supplied whenthe first sampling signal (S1) is activated within past n-times matchesthe row address (XADD) supplied when the first sampling signal (S1) iscurrently activated, the second sampling signal S2 can be activated. Inother words, the access to the word lines (WL) can be intermittentlymonitored, and, if the access to the same word line WL is captured atleast a predetermined number of times (e.g., two or more times) within apredetermined period of time, the second sampling signal (S2) can beactivated.

The second sampling signal S2 can be supplied to a latch circuit 410.The latch circuit 410 can be configured to latch the current row address(XADD) in response to the second sampling signal (S2). The latch circuit410 can output the latched result to a control circuit 420 as a rowaddress (HitXADD) that corresponds to the word line WL having a highaccess frequency. The control circuit 420 can be configured to convertthe row address (HitXADD) output from the latch circuit 410 to a rowaddress RXADD of the word line WL affected by the highly-frequentaccess. In other words, the row address (HitXADD) can be an aggressoraddress, and the row address (RXADD) can be a victim address, such asfor the word line (WL) adjacent to or within a predetermined distancefrom the word line (WL) accessed by the aggressor address. The controlcircuit 420 can also be configured to generate a trigger (e.g., theinternal detection flag) based on detecting the repeated-accesscondition.

For illustrative purposes, the detection circuit 400 is shown asdetecting repeated row-accesses (e.g., row hammer conditions). However,it is understood that the detection circuit 400 can be configured todetect other repetitive access conditions, such as for columns, otherlocations, and/or other patterns.

FIG. 5 is an example timing diagram 500 in accordance with an embodimentof the present technology. The timing diagram 500 illustrates an examplereactionary process implemented by the host (e.g., the host 102 of FIG.1 and/or the host 202 of FIG. 2) in response to a scheduling output 502from the memory (e.g., the memory system 104 of FIG. 1, the memorysystem 204 of FIG. 2, and/or one or more devices therein). As anillustrative example, the scheduling output 502 can correspond to anALERT signal associated with parity errors. The timing diagram 500 canillustrate an error-handling or recovery process implemented by the hostin response to the ALERT signal.

In some embodiments, the memory device can be configured to ignore ornot execute a predetermined number of commands/operations followingdetection of an error or a predetermined condition (e.g.,repeated-access). For example, the memory device can detect at time Ta1a triggering condition, such as a parity error or a row hammer, andsubsequently ignore the received valid commands (e.g., at Ta2, Tb0,etc.). The memory device can be configured to generate the schedulingoutput 502 by setting the ALERT signal low within a predetermined periodfollowing the detection, thereby notifying the host of the detectedcondition. Accordingly, the host can be configured to resend the ignoredcommands (e.g., a predetermined number of commands preceding and/orfollowing the scheduling output 502).

Based on the error recover process of the host, the memory device candetermine an internal-operation window 512 for executing thememory-internal operations (e.g., refreshes). In other words, since thehost is configured to resend a known amount of commands, the memorydevice can secure a corresponding time window to execute thememory-internal operations. The memory device can determine theinternal-operation window 512 based on the determination and/or thescheduling output 502. In some embodiments, the memory device candetermine internal-operation window 512 to start from the determination,the generation of the scheduling output 502, or a predetermined numberof cycles subsequent thereto. In some embodiments, the memory device candetermine the internal-operation window 512 to extend into or throughthe scheduling output 502 (e.g., tPAR_ALERT_PW) and/or a followingwindow (e.g., recovery window, tRP). In some embodiments, theinternal-operation window 512 extends up to a predetermined time for therecovery process (e.g., Te0), such as when execution of commands arerequired.

FIG. 6 is a flow diagram illustrating an example method 600 of operatingan apparatus (e.g., the system 100 of FIG. 1, the system 200 of FIG. 2,and/or one or more devices therein) in accordance with an embodiment ofthe present technology. The method 600 can be for operating the host 102of FIG. 1, the host 202 of FIG. 2, the memory device 104 of FIG. 1, theregister device 144 of FIG. 1, the storage device 242 of FIG. 2, and/orthe device 300 of FIG. 3 to manage the memory-internal operations, suchas refresh operations.

At block 602, the apparatus (e.g., the host) can initiate a memoryoperation, such as a write, a read, or a refresh. The host cancommunicate one or more commands, addresses, and/or data associated withthe memory operation to the memory device (via, e.g., one or moreconnections illustrated in FIG. 1 and/or FIG. 2). At block 652, theapparatus (e.g., the memory device) can receive the informationassociated with the memory operation.

At block 654, the apparatus (e.g., the memory device) can determinewhether the received memory operation satisfies a predeterminedcondition. For example, the memory device can use the detection circuit154 of FIG. 1 and/or the detection circuit 254 of FIG. 2 to track anumber of accesses to one or more addresses/regions within a givenduration. The memory device can detect the triggering condition, such asa repeated access (e.g., row hammer condition), when the tracked numbermatches or exceeds a predetermined threshold. When the received memoryoperation does not satisfy the predetermined condition, such asillustrated at block 656, the apparatus (e.g., the memory device) canimplement the commanded memory operation. Accordingly, the apparatus cancontinue operation and initiate/execute a subsequent memory operation.

When the received memory operation satisfies the predeterminedcondition, such as illustrated at block 658, the apparatus (e.g., thememory device) can generate a schedule output. For example, the memorydevice can generate the schedule output as a mechanism (via, e.g., asignal and/or data sent to the host) to secure a time window (e.g., theinternal-operation window 512 of FIG. 5) during which the host pausescommands/initiations of scheduled operations. Accordingly, the memorydevice can execute memory-internal operations during the secured timewindow.

In some embodiments, as illustrated at block 660, the apparatus cangenerate the schedule output by reporting increased temperature levels.For example, the memory device can report to the host (e.g., per regularreporting timing) a temperature level that is higher than the actualcurrent temperature. Accordingly, the host can increase the refresh rateaccording to the reported temperature level, thereby increasing thefrequency of the refresh operations and the corresponding time windows.In some embodiments, the memory device can determine a measure (e.g., aduration, a rating, an amount, an access frequency, etc.) associatedwith the internal operations. The memory device can increase thereported temperature level according to the determined measure.

In some embodiments, as illustrated at block 662, the apparatus cangenerate the schedule output by setting an alert (e.g., a signal or aflag) independent of the represented condition. For example, the memorydevice can set the ALERT #for DDR4/5 connections. Based on the alert,the memory device can report to the host one or more errors independentof the actual occurrence of such errors. For example, even without theoccurrence of corresponding error conditions, the memory device can setthe alert signal and predetermined bits to represent data write/read CRCerrors, command CA parity errors, and/or other errors.

In some embodiments, as illustrated at block 662, the apparatus cangenerate the schedule output by adjusting data sent to the host. Forexample, the memory device can adjust one or more bits of read data thatis sent to the host.

At block 604, the apparatus (e.g., the host) can receive the signaland/or the data associated with the schedule output. At block 606, theapparatus can determine the condition (e.g., the scheduling conditionand/or the error condition) associated with the received signal/data. Atblock 608, the apparatus can implement the reaction. As an illustrativeexample, the host can increase the refresh rate (by, e.g., a factor of2, 4, etc.) in response to determination of increased temperature of thememory device. Also, the host can retry write/read, resend commands,and/or implement recovery processes in response to determination ofcommunication errors. Further, the host can retry reads in response todetermining errors in the read data. In implementing the reactions, thehost can pause implementation of subsequently scheduled operations for atime window that corresponds to the determined condition.

At block 670, the apparatus (e.g., the memory device) can determine theduration of the time window based on the determined condition and/or theschedule output. For example, the memory device can determine thewindows (e.g., margins) associated with the increased refreshes thatresult from the increased temperature report. Also, the memory devicecan determine the internal-operation window 512 associated with retryingwrite/read, resending commands, and/or implementing recovery processes.The internal-operation window 512 for various different schedule outputscan be predetermined according to standards and/or host specifications.Accordingly, the memory device can use a lookup table or other storedinformation to determine the internal-operation window 512.

At block 672, the apparatus (e.g., the memory device) can use theinternal-operation window 512 to initiate and/or execute memory-internalprocesses. For example, the memory device can execute refresh operations(e.g., RHR) during the secured operation window 512. Accordingly, theapparatus can dynamically adjust the scheduling of memory-internaloperations based on real-time conditions without being limited tomargins within/between host scheduled operations. In other words, thememory device can use the schedule output to interact with the host andsecure the internal-operation window 512 for executing thememory-internal operations. Thus, the apparatus can reduce errorsassociated with insufficient durations to implement memory-internaloperations and/or infrequent implementations thereof.

FIG. 7 is a schematic view of a system that includes an apparatus inaccordance with embodiments of the present technology. Any one of theforegoing apparatuses (e.g., memory devices) described above withreference to FIGS. 1-6 can be incorporated into any of a myriad oflarger and/or more complex systems, a representative example of which issystem 780 shown schematically in FIG. 7. The system 780 can include amemory device 700, a power source 782, a driver 784, a processor 786,and/or other subsystems or components 788. The memory device 700 caninclude features generally similar to those of the apparatus describedabove with reference to FIGS. 1-6, and can therefore include variousfeatures for performing a direct read request from a host device. Theresulting system 780 can perform any of a wide variety of functions,such as memory storage, data processing, and/or other suitablefunctions. Accordingly, representative systems 780 can include, withoutlimitation, hand-held devices (e.g., mobile phones, tablets, digitalreaders, and digital audio players), computers, vehicles, appliances andother products. Components of the system 780 may be housed in a singleunit or distributed over multiple, interconnected units (e.g., through acommunications network). The components of the system 780 can alsoinclude remote devices and any of a wide variety of computer readablemedia.

From the foregoing, it will be appreciated that specific embodiments ofthe technology have been described herein for purposes of illustration,but that various modifications may be made without deviating from thedisclosure. In addition, certain aspects of the new technology describedin the context of particular embodiments may also be combined oreliminated in other embodiments. Moreover, although advantagesassociated with certain embodiments of the new technology have beendescribed in the context of those embodiments, other embodiments mayalso exhibit such advantages and not all embodiments need necessarilyexhibit such advantages to fall within the scope of the technology.Accordingly, the disclosure and associated technology can encompassother embodiments not expressly shown or described herein.

In the illustrated embodiments above, the apparatuses have beendescribed in the context of DRAM devices. Apparatuses configured inaccordance with other embodiments of the present technology, however,can include other types of suitable storage media in addition to or inlieu of DRAM devices, such as, devices incorporating NAND-based orNOR-based non-volatile storage media (e.g., NAND flash), magneticstorage media, phase-change storage media, ferroelectric storage media,etc.

The term “processing” as used herein includes manipulating signals anddata, such as writing or programming, reading, erasing, refreshing,adjusting or changing values, calculating results, executinginstructions, assembling, transferring, and/or manipulating datastructures. The term data structures includes information arranged asbits, words or code-words, blocks, files, input data, system generateddata, such as calculated or generated data, and program data. Further,the term “dynamic” as used herein describes processes, functions,actions or implementation occurring during operation, usage ordeployment of a corresponding device, system or embodiment, and after orwhile running manufacturer's or third-party firmware. The dynamicallyoccurring processes, functions, actions or implementations can occurafter or subsequent to design, manufacture, and initial testing, setupor configuration.

The above embodiments are described in sufficient detail to enable thoseskilled in the art to make and use the embodiments. A person skilled inthe relevant art, however, will understand that the technology may haveadditional embodiments and that the technology may be practiced withoutseveral of the details of the embodiments described above with referenceto FIGS. 1-7.

We claim:
 1. An apparatus, comprising: a detection circuit configured todetect a condition associated with two or more accesses to a memoryaddress or a memory region within a predetermined duration; and ascheduling circuit coupled to the detection circuit, the schedulingcircuit configured to: generate a scheduling output based on thedetected condition, wherein the scheduling output is communicated to ahost coupled to the apparatus for securing a scheduled duration ofinactivity for the apparatus, and trigger execution of one or morememory-internal operations during the scheduled duration.
 2. Theapparatus of claim 1, wherein the one or more memory-internal operationsinclude one or more row hammer refresh operations.
 3. The apparatus ofclaim 1, wherein the scheduling output represents a command addressparity error, wherein the scheduling output is independent of an actualcommand address parity.
 4. The apparatus of claim 1, wherein thescheduling output represents a cyclic redundancy check (CRC) error,wherein the scheduling output is independent of an actual CRC data. 5.The apparatus of claim 1, wherein the scheduling output is apredetermined state or value for an alert signal that reports an errorcondition in response to the detected condition, wherein the schedulingoutput is independent of the condition.
 6. The apparatus of claim 5,wherein the scheduling output corresponds to an ALERT #signal accordingto a Double Data Rate (DDR) protocol.
 7. The apparatus of claim 1,wherein the scheduling output includes one or more flipped data (DQ)bits.
 8. The apparatus of claim 7, wherein the scheduling output is fortriggering an error correction process at the host.
 9. The apparatus ofclaim 1, wherein the scheduling output is configured to report atemperature level higher than an actual temperature reading for theapparatus.
 10. The apparatus of claim 1, further comprising a registerdevice.
 11. The apparatus of claim 10, wherein the apparatus comprises aregister clock driver.
 12. The apparatus of claim 1, wherein theapparatus further comprises a memory array having a plurality of memorycells.
 13. The apparatus of claim 1, wherein the apparatus comprises adynamic random-access memory (DRAM).
 14. The apparatus of claim 1,wherein the scheduling circuit includes a transistor connected to acorresponding connection port and the scheduling output, wherein thetransistor is configured to force an output level at the connection portto a predetermined level when the scheduling output represents thedetected condition.
 15. A method of operating an apparatus, the methodcomprising: receiving a command for an operation from a host coupled tothe apparatus; detecting a condition based on the command, wherein thecondition is associated with two or more accesses to a memory address ora memory region within a predetermined duration; generating a schedulingoutput based on the detected condition, wherein the scheduling output iscommunicated to the host for securing a scheduled duration of inactivityfor the apparatus; and initiating one or more internal operations duringthe scheduled duration.
 16. The method of claim 15, further comprisingexecuting the one or more internal operations during the scheduledduration, wherein the one or more internal operations include one ormore row hammer refresh operations.
 17. The method of claim 15, whereingenerating the scheduling output includes communicating to the host asignal representative of an error condition in response to the detectedcondition, wherein the scheduling output is independent of the errorcondition.
 18. The method of claim 15, wherein generating the schedulingoutput includes flipping one or more data (DQ) bits communicated withthe host.
 19. The method of claim 15, wherein generating the schedulingoutput includes reporting a temperature level higher than an actualtemperature reading for the apparatus.
 20. A system, comprising: a hostconfigured to command a memory operation; and a memory device coupled tothe host, the memory device configured to: detect a condition based onthe memory operation, wherein the condition is associated with two ormore accesses to a memory address or a memory region within apredetermined duration; generate a scheduling output based on thedetected condition, wherein the scheduling output is communicated to thehost for securing a scheduled duration of inactivity for the memorydevice; and initiate one or more memory-internal operations during thescheduled duration; wherein: the host is configured to pause scheduledoperations for the scheduled duration including and/or subsequent to thememory operation.
 21. The system of claim 20, wherein: the schedulingoutput represents an error condition; the memory device is configuredto: generate the scheduling output based on the detected condition andindependent of the error condition, and execute the one or morememory-internal operations during the scheduled duration; and the hostis configured to implement an error recovery process during thescheduled duration based on the scheduling output from the memorydevice.